1. Field of the Invention
The present invention relates to a Metal-Insulator-Semiconductor (hereinafter referred to as MIS) type semiconductor device, and specifically relates to a MIS transistor. More specifically the present invention relates to a thin-film state MIS type semiconductor device, a thin-film transistor (hereinafter referred to as TFT) formed on an insulating substrate, and above all relates to a MIS type semiconductor device having a so-called inverse stagger type structure, a channel forming region of which is positioned above a gate electrode. The application fields of the present invention are semiconductor integrated circuit formed on an insulating substrate, for example an active matrix type circuit used in a liquid crystal display, a driving circuit for an image sensor and the like.
2. Description of the Related Art
In recent years, a thin-film state MIS type semiconductor device formed on an insulating substrate has been used. For example an active matrix type liquid crystal display etc. have been known. There are two kinds of active matrix type circuit which are on the present market, one is a TFT using type and the other is such diode as a MIM (Metal Insulator Metal) using type. Particularly, the former has been successfully manufactured recently because it has given a high quality image.
As an active matrix circuit using TFT, two sorts of TFT, which employ such polycrystal semiconductor as polycrystal silicon and such amorphous semiconductor as amorphous silicon, have been known. The former has a difficulty in preparation for a large picture owing to its preparing process, and then the latter, which can be prepared at a temperature of 350 or below, has been mainly used for a large picture.
FIG. 2 shows a preparing process of a conventional amorphous silicon TFT (an inverse stagger type). As the substrate 201, such heat resistant and non-alkali glass as Corning 7059 is used. Since the maximum temperature of preparing process for the amorphous silicon TFT is around 350, it is required that the material therefor be resistant up to this temperature. Especially in case of a liquid crystal display panel, the material is in need of a heat resistant property and a high glass transition temperature not to be distorted by heat treatment. The Corning 7059 can meet for the need, as the glass transition temperature thereof is a little lower than 600.
Also, in order to stabilize an operation of TFT, it is not desirable that such movable ion as Na is contained in a substrate. There is no problem with the Corning 7059 having quite low content of alkalies, but it is necessary to form such passivation film as a silicon nitride film or an aluminum oxide film so that the movable ions in a substrate do not invade into TFT, in case a lot of Na etc. is contained in the substrate.
Next, a film is formed using materials such as aluminum or tantalum,a patterning is effected using the mask 1 and the gate electrode 202 is formed. In particular, in order to prevent a short circuit between the gate electrode wiring and the upper wiring thereof, it is recommended to form the oxide film 203 on this gate electrode surface. An anode oxidation method is chiefly employed in the forming way of the oxide film.
Then, the gate insulating film 204 is formed. As the gate insulating film, a silicon nitride is generally used. But a silicon oxide can be also used, and a silicide mixed with nitrogen and oxygen in a free amount ratio can be used. Further both of the single layer and the polylayer films can be available. When a silicon nitride film is used as the gate insulating film and a plasma CVD method is applied, the process temperature becomes 350, the maximum temperature of the process, the situation of which is shown in FIG. 2(A).
Next, an amorphous silicon film is formed, it is necessary to raise a temperature of the substrate up to 250 to 300, in case a plasma CVD method is used. The film thickness is desired as thin as possible, it is generally to be 10 to 100 nm, and preferably to be 10 to 30 nm. The amorphous silicon region 205 is formed by patterning with the mask 2 which later will become a channel forming region of TFT. The situation so far is shown in FIG. 2(B).
Further, a silicon nitride film is formed all over the surface, which is patterned with the mask 3 to get the etching stopper 206. This stopper is prepared so that the amorphous silicon region 205 for a channel forming region will not be etched by mistake in a later process, because the amorphous silicon region 205 is as thin as 10 to 100 nm as aforementioned. Also, since the amorphous silicon region under part of the etching stopper functions as a channel forming region, the etching stopper is designed to overlap with the gate electrode as fully as possible. A conventional mask alignment, however, gives a somewhat discrepancy, then the patterning is carried out so as to achieve an enough overlapping with the gate electrode.
After that, N-type or P-type conductivity silicon film is formed. An ordinary amorphous silicon TFT is N-type one. This silicon film is prepared to be a microcrystal state, as an amorphous silicon is too low in a conductivity. N-type microcrystal silicon film can be prepared at a temperature of 350 or below by a plasma CVD method. But it is not low enough in resistance, and then the thickness of 200 nm or more was required. P-type microcrystal silicon film was too big in resistance to be used, it was, therefore, difficult to prepare a P-channel type TFT with an amorphous silicon.
The silicon film prepared in this way is patterned using the mask 4 to form N-type microcrystal silicon region 207. The situation so far is shown in FIG. 2(C), in which a function of TFT can not be realized, as (N-type) microcrystal silicon film is connected with itself on the etching stopper. It is, therefore, necessary to separate the connection, and the groove 208 is formed by separating the connection using the mask 5. It is feared that even the amorphous silicon region 205 as a base is etched out making a mistake, if there is no etching stopper in this case. This is caused by the reason that the microcrystal silicon region 207 is from several to some ten times or more as thick as the amorphous silicon region thereunder. Afterward, the wiring 209 and the pixel electrode 210 are prepared, using the masks 6 and 7 by a known method, the situation of which is shown in FIG. 2(D).
In the method stated above, so many seven sheets of mask are used, and it is worried that a yield will be lowered. Therefore, a decreasing way of the number of masks has been proposed as will be described in the following; Firstly, a gate electrode part is patterned on a substrate using the first mask. Then, a gate insulating film is formed, further, an amorphous silicon film and a silicon nitride film (later will be an etching stopper) are continuously formed. Next, an etching stopper is formed by etching only the silicon nitride film in a way of self-alignment, using a gate electrode as a mask and exposing from the back. Then, thereon a microcrystal silicon film is formed, and a TFT region including a groove over the channel(corresponds to the numeral 208 in FIG. 2) is formed using the second mask. Afterward, a wiring and an electrode are formed using the third and fourth masks. Finally, the equivalent one as shown in FIG. 2(D) can be obtained. In such way, the number of masks can be reduced by three utilizing a self-alignment process.
Thus formed TFT is very uneven, as distinct from FIG. 2(D). This is mainly derived from the gate electrode part (contains gate electrode oxide 203), the etching stopper, and the microcrystal silicon region. A total 800 nm of unevenness will happen, supposing that each thickness of the gate electrode part, the etching stopper, and the microcrystal silicon region 206 is 300 nm, 200 nm, and 300 nm respectively. For example in case where TFT is used in an active matrix circuit of a liquid crystal display panel, the thickness of a cell is 5 to 6m and is controlled to an accuracy of 0.1m or less. Under such condition, even 1m of unevenness will cause a remarkable defect to a thickness uniformity of a cell.
However, any of these factors to cause the unevenness of TFT can not be cut down easily. Namely, the thinner a gate electrode part is, the higher the resistance of gate electrode wiring will be. On the other hand, in order to keep the constant resistance, widening of a gate electrode (i.e. lengthening of a channel) will bring about not only lowering of TFT operation speed but also large area of TFT part, which will cause an aperture ratio to be lowered in case TFT is used in a liquid crystal display.
Also, in case the etching stopper is thin, there is a possibility that even an amorphous silicon region underlying a microcrystal silicon region will be in error to be etched, during the etching of the microcrystal silicon region, and then a yield will be lowered. Further, in case the microcrystal silicon region is thin, the source/drain region resistance of TFT will be increased and ON/OFF ratio of TFT will be decreased.
Still more, the etching stopper will remain as it is, at the time of completion of TFT. The silicon nitride film used for the etching stopper has a nature to trap electric charge. If electric charge is trapped therein for some reason, an unwilling channel will be formed in the amorphous silicon region 205 thereunder, which will cause a leak of drain current. To avoid this problem, it is necessary to cause the etching stopper to be two layer structures of silicon oxide and silicon nitride. In this case, it is needed that the silicon oxide film be also thick enough, and preferably be 100 nm thick or more.